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TB62D612FTG 2012-07-23 1 toshiba bi-cmos integrated circuit silicon monolithic TB62D612FTG 24-channel constant-current led dr iver of the 3.3-v and 5-v power supply voltage operation the TB62D612FTG is a constant-current driver designed for led and led display lighting. the TB62D612FTG incorporates twenty-four channels of seven-bit pwm dimming controllers and constant-current drivers. twenty-four constant-current drivers are divided into three blocks, each consisting of three drivers, and the output current of each can be independent ly adjusted by the relevant external resistor. the TB62D612FTG is controlled using t he sda and sclk input signals, and capable of high-speed data transfers. the TB62D612FTG can be set address with id terminal. (up to 64 address) high-speed processing is capable by applying bi-cmos process. the TB62D612FTG operates with a supply voltage of 3.3 v or 5 v. 1 features ? power supply voltages: v cc = 3.3 v/5 v ? output drive capability and output count: 80 ma (max) 24 channels ? constant-current output range: 5 to 40 ma ? voltage applied to constant-current output terminals: 0.4 v(min) (i out = 5 to 40 ma) ? designed for common-anode leds ? the input interface is controlled by the sda and sclk signal lines ? thermal shutdown (tsd) ? logical input signal voltage level: 3.3-v and 5-v cmos interfaces (schmitt trigger input) ? maximum output voltage: 28 v ? incorporating pwm control circuitry: provides seven-bit pwm control. ? driver identification: up to 64 drivers can be controlled individually. ? operating temperature range: t opr = ? 40 to 85 c ? package: p-wqfn36-0606-0.50-001 ? constant-current accuracy output voltage current accuracy between channels current accuracy between ics output current 0.4 v 3.0% 6.0% 15 ma p-wqfn36-0606-0.50-001 weight: 0.083 g ( typ.)
TB62D612FTG 2012-07-23 2 2 pin assignment (top view) 3 block diagram 1 2 top view 3 4 5 6 10 11 12 13 14 15 16 17 18 19 22 20 21 23 26 24 25 27 28 32 31 30 29 36 35 34 33 7 8 9 /outg5 /outb5 /outb2 /outr3 /outr6 /outg6 /outb6 /outr7 /outg7 /outb7 rext-r /outg2 /outr2 /outb1 /outg1 /outr1 /outb0 /outg0 /outr0 reset /outg3 /outb3 pgnd /outr4 /outg4 /outb4 /outr5 rext-g sclk sda vcc id2 id1 id0 gnd rext-b pwm(7bit) data buffer sda sclk vcc /outr0 rext-r pwm(7bit) /outr7 pwm(7bit) /outg0 pwm(7bit) /outg7 pwm(7bit) /outb0 pwm(7bit) /outb7 rext-b rext-g tsd clk generation id0 id1 id2 gnd adress configration logic processing reset constant- current driver constant- current driver constant- current driver constant- current driver constant- current driver constant- current driver pgnd
TB62D612FTG 2012-07-23 3 4 terminal description pin no symbol function 1 /outb2 constant-current output terminal (open-collector type) 2 /outr3 constant-current output terminal (open-collector type) 3 /outg3 constant-current output terminal (open-collector type) 4 /outb3 constant-current output terminal (open-collector type) 5 pgnd power ground pin 6 /outr4 constant-current output terminal (open-collector type) 7 /outg4 constant-current output terminal (open-collector type) 8 /outb4 constant-current output terminal (open-collector type) 9 /outr5 constant-current output terminal (open-collector type) 10 /outg5 constant-current output terminal (open-collector type) 11 /outb5 constant-current output terminal (open-collector type) 12 /outr6 constant-current output terminal (open-collector type) 13 /outg6 constant-current output terminal (open-collector type) 14 /outb6 constant-current output terminal (open-collector type) 15 /outr7 constant-current output terminal (open-collector type) 16 /outg7 constant-current output terminal (open-collector type) 17 /outb7 constant-current output terminal (open-collector type) 18 rext-r external resistor pin for output current configuration (/outr0 to /outr7) 19 rext-g external resistor pin for output current configuration (/outg0 to /outg7) 20 rext-b external resistor pin for output current configuration (/outb0 to /outb7) 21 gnd ground pin 22 id0 id configuration pin (note 1) 23 id1 id configuration pin (note 1) 24 id2 id configuration pin (note 1) 25 vcc power supply terminal 26 sda serial data input terminal 27 sclk serial clock input terminal 28 reset reset signal input. (setting this pi n high resets internal data.) (note 1) 29 /outr0 constant-current output terminal (open-collector type) 30 /outg0 constant-current output terminal (open-collector type) 31 /outb0 constant-current output terminal (open-collector type) 32 /outr1 constant-current output terminal (open-collector type) 33 /outg1 constant-current output terminal (open-collector type) 34 /outb1 constant-current output terminal (open-collector type) 35 /outr2 constant-current output terminal (open-collector type) 36 /outg2 constant-current output terminal (open-collector type) note 1: after the reset is released, it should be ensured that ids (slave addresses) are properly configured.
TB62D612FTG 2012-07-23 4 5 equivalent circuits for inputs and outputs sda and sclk terminals reset terminals constant-current output terminals id0, id1, and id2 terminals vcc gnd /outr0 to /outr7 /outg0 to /outg7 /outb0 to /outb7 pgnd vcc gnd reset vcc gnd comparison sda sclk id0 id1 id2
TB62D612FTG 2012-07-23 5 6 programming the TB62D612FTG the TB62D612FTG can be programmed by the sda and sclk signals. the TB62D612FTG should be programmed using one of the followi ng formats: (1) serial packet fo rmat in normal programming mode or (3) serial packet format in special mode. (1) serial packet format in normal programming mode typical start command [11111111] slave address 8 bits sub-address (channel select) 8 bits data byte (pwm :w configuration) 8 bits period command [10000001] ? normal programming mode should be set as the following flow. ?start command? ? ?slave address? ? ?sub-address? ? ?data byte? ? ?period command? as for example of data input, refer to page8. ? input data from sda signal is written to the shift register at the rising edge of sclk every 8 bit. this data is transferred at the falling edge of the eighth clk. so, at the eighth cl k, data should be inputted to the falling e dge. block diagram of data setting part in case of period command :a:?:? :a:?: : data is transferred at the falling edge of the eighth sclk. data is written to the shift register at the rising edge of the sclk. data is transferred at the falling edge of the eighth sclk. cac|cnc^chc|cpcb :?:? cac|cnc^chc|cpcb :?:? cac|cnc^chc|cpcb :?:? cac|cnc^chc|cpcb :?:? cac|cnc^chc|cpcb :?:? cac|cnc^chc|cpcb :?:? cac|cnc^chc|cpcb :?:? cac|cnc^chc|cpcb :?:? :?:1::? :?:1::? :?:1::? :?:1::? :?:1::? :?:1::? :?:1::? :?:1::? bpb?b]b?bbt :?:1::? btbbb?b]b?bbt :?:1::? :?b?b~b?brb?b?bbsbtbz &3
lbnb?b?b? :?:1::? :?:1::? :?:1::? :?:1::? :?:1::? :?:1::? :?:1::? :?:1::? ccc :?:? ccc :?:? ccc :?:? ccc :?:? ccc :?:? ccc :?:? ccc :?:? ccc :?:? :?:1::? :?:1::? :?:1::? :?:1::? :?:1::? :?:1::? :?:1::? :?:1::? :a:?:? :a:?:: :?b?b~b? bfbab?bz 8bit shift-resister 8bit shift-register slave address sub address data byte data byte data byte r0 data byte g0 data byte b0 data byte r1 data byte r7 data byte g7 data byte b7 terminal command 8 bit counter
TB62D612FTG 2012-07-23 6 (2) data settings a) slave addresses input voltages and logic states of the id0, id1 and id2 pins are determined as follows. (high order bit = 0. low order bi t = 0 (except of all selection)) vcc =?11?, 2/3vcc =?10?, 1/3vcc = "01?, gnd =?00? slave addresses id2 id1 id0 00000000 gnd gnd gnd 00000010 gnd gnd 1/3vcc 00000100 gnd gnd 2/3vcc 00000110 gnd gnd vcc 00001000 gnd 1/3vcc gnd 00001010 gnd 1/3vcc 1/3vcc 00001100 gnd 1/3vcc 2/3vcc 00001110 gnd 1/3vcc vcc 00010000 gnd 2/3vcc gnd 00010010 gnd 2/3vcc 1/3vcc 00010100 gnd 2/3vcc 2/3vcc 00010110 gnd 2/3vcc vcc 00011000 gnd vcc gnd 00011010 gnd vcc 1/3vcc 00011100 gnd vcc 2/3vcc 00011110 gnd vcc vcc 00100000 1/3vcc gnd gnd 00100010 1/3vcc gnd 1/3vcc 00100100 1/3vcc gnd 2/3vcc 00100110 1/3vcc gnd vcc 00101000 1/3vcc 1/3vcc gnd 00101010 1/3vcc 1/3vcc 1/3vcc 00101100 1/3vcc 1/3vcc 2/3vcc 00101110 1/3vcc 1/3vcc vcc 00110000 1/3vcc 2/3vcc gnd 00110010 1/3vcc 2/3vcc 1/3vcc 00110100 1/3vcc 2/3vcc 2/3vcc 00110110 1/3vcc 2/3vcc vcc 00111000 1/3vcc vcc gnd 00111010 1/3vcc vcc 1/3vcc 00111100 1/3vcc vcc 2/3vcc 00111110 1/3vcc vcc vcc 01000000 2/3vcc gnd gnd 01000010 2/3vcc gnd 1/3vcc 01000100 2/3vcc gnd 2/3vcc 01000110 2/3vcc gnd vcc 01001000 2/3vcc 1/3vcc gnd 01001010 2/3vcc 1/3vcc 1/3vcc 01001100 2/3vcc 1/3vcc 2/3vcc 01001110 2/3vcc 1/3vcc vcc 01010000 2/3vcc 2/3vcc gnd 01010010 2/3vcc 2/3vcc 1/3vcc 01010100 2/3vcc 2/3vcc 2/3vcc 01010110 2/3vcc 2/3vcc vcc 01011000 2/3vcc vcc gnd 01011010 2/3vcc vcc 1/3vcc 01011100 2/3vcc vcc 2/3vcc 01011110 2/3vcc vcc vcc 01100000 vcc gnd gnd 01100010 vcc gnd 1/3vcc 01100100 vcc gnd 2/3vcc
TB62D612FTG 2012-07-23 7 01100110 vcc gnd vcc 01101000 vcc 1/3vcc gnd 01101010 vcc 1/3vcc 1/3vcc 01101100 vcc 1/3vcc 2/3vcc 01101110 vcc 1/3vcc vcc 01110000 vcc 2/3vcc gnd 01110010 vcc 2/3vcc 1/3vcc 01110100 vcc 2/3vcc 2/3vcc 01110110 vcc 2/3vcc vcc 01111000 vcc vcc gnd 01111010 vcc vcc 1/3vcc 01111100 vcc vcc 2/3vcc 01111110 vcc vcc vcc 0xxxxxx1 all select b) sub-addresses output channel set / all channels set / special mode set in output channel set, a channel which defines pwm configuratio n is selected. in all channels set, pwm is configured for all channels. special mode sets this mode according to the description in page 8. 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0bit ch set 0 0 0 0 0 0 1 0 /outr0 0 0 0 0 0 1 0 0 /outg0 0 0 0 0 0 1 1 0 /outb0 0 0 0 0 1 0 0 0 /outr1 0 0 0 0 1 0 1 0 /outg1 0 0 0 0 1 1 0 0 /outb1 0 0 0 0 1 1 1 0 /outr2 0 0 0 1 0 0 0 0 /outg2 0 0 0 1 0 0 1 0 /outb2 0 0 0 1 0 1 0 0 /outr3 0 0 0 1 0 1 1 0 /outg3 0 0 0 1 1 0 0 0 /outb3 0 0 0 1 1 0 1 0 /outr4 0 0 0 1 1 1 0 0 /outg4 0 0 0 1 1 1 1 0 /outb4 0 0 1 0 0 0 0 0 /outr5 0 0 1 0 0 0 1 0 /outg5 0 0 1 0 0 1 0 0 /outb5 0 0 1 0 0 1 1 0 /outr6 0 0 1 0 1 0 0 0 /outg6 0 0 1 0 1 0 1 0 /outb6 0 0 1 0 1 1 0 0 /outr7 0 0 1 0 1 1 1 0 /outg7 0 0 1 1 0 0 0 0 /outb7 0 1 0 0 0 0 0 0 all channel select 0 1 1 0 0 0 0 0 special mode (bits of high order and low order must be zero.) c) data bytes (pwm configuration) data bytes set pwm diming. (low order bit must be zero.) 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0bit pwm dimming (for reference only) 0 0 0 0 0 0 0 0 off(default) 0 0 0 0 0 0 1 0 1/127 0 0 0 0 0 1 0 0 2/127 ??? 1 1 1 1 1 1 0 0 126/127 1 1 1 1 1 1 1 0 127/127 note: any data other than those specif ied above must not be programmed.
TB62D612FTG 2012-07-23 8 (3) serial packet fo rmat in special mode when data of 01100000 is input to the sub address, the operation moves to the special mode where all channels are selected in order. data of 24 channels should be input. (if data of more than 24 channels are provi ded, the 25th and subsequent data are treated as invalid. if data of less than 24 channels are provided, those data are written to the channels in order and the remaining channels retain the previous data.) to return to the normal mode, input data from the start command (all?h?8bit). in case of using this mode configuration, volume of data can be omitted. (4) input example of data set a) in case 127 pwm clocks/127(100% on) are confi gured to all channels of slave address 00h. b) in case 127 pwm clocks/127(100% on) are configured to only /outr0 pin and /outb7 pin of slave address 02h. as for other than /outr0 and /outb7 terminals in above configurat ion, output pins which have al ready outputted data continue to output prior data. (in case of changing onl y outputting data which is required to be changed, this configuration is valid.) s tart condition [11111111] sl ave a ddresses (special mode set [01100000] outr7 data outr0 outg0 outb0 outr1 outb6 p er i o d command [10000001] outg7 outb7 data data data data data data data s u b -a dd ress (11111111) sl ave addresses (00000010) s u b -a dd ress (r0) (00000010) data bytes (11111110) s u b -a dd ress (b7) (00110000) data bytes (11111110) p er i o d command (10000001) s tart command (00000000) sub address(r0) (00000010) (11111110) (00000100) (11111110) (00000110) st ar t command slave address (11111111) (11111110) ( 00001010) ( 11111110) ( 00001100) (11111110) data bytes (00001000) sub address(r1) data bytes sub address(g1) data bytes sub address(b1) (11111110) data bytes (11111110) data bytes sub address(b0) data bytes sub address(g0) data bytes (00101100) sub address(r7) (11111110) data bytes (00101110) sub address(g7) data bytes (11111110) (00110000) sub address(b7) (10000001) period command
TB62D612FTG 2012-07-23 9 (5) data settings and timing of outputs note data is transferred by synchronizing period command (10000001) with the internal pwm counter (max). so, if data is inputted aft er the period command is inputted and before the internal pwm counter counts its maximum, data which is inputted after period input is not accepted. in order to set data to the same id (ic), next data should be inputted after 3 ms which corresponds to 128 internal pwm clocks is passed since the period command is inputted. however, in or der to set data to the different id, terminal of 3 ms which corresponds to 128 in ternal pwm clocks should not be taken. data is written to the shift register at the rising edge of sclk every 8 bits, and is transferred at the falling edge of eighth clk. so, data s hould be inputted to the falling edge at the eighth clk. counter max. prior data data transfer period command no ye s
TB62D612FTG 2012-07-23 10 (6) example of data input to the same id a) in case data a is inputted up to the rising edge of 127 internal pwm clocks. outputting data a starts at the rising edge of one internal pwm clock. inputting is invalid from the rising edge of 127 internal pwm cl ocks to the rising edge of one internal pwm clock which is just after these 127 pwm clocks. b) in case data a is inputted after t he rising edge of 127 internal pwm clocks. outputting data a does not start at the risi ng edge of one internal pwm clock just afte r the data a is inputted. it starts at t he next rising edge of one internal pwm clock. inputting is invalid from the data a (period) input to the rising edge of after the next one internal pwm clock. c) in case data b is inputted afte r data of pattern 1 starts outputting. outputting data a starts at the rising edge of one internal pwm clock just after the data a is inputted. outputting data b star ts at the rising edge of one internal pwm clock which is just after the data b input. inputting is invalid in the following term. from the rising edge of 127 internal pwm clocks which are just after the data a is inputted to the rising edge of one internal pwm clock which is just after these 127 clocks. from the rising edge of 127 internal pwm clocks which is just after the data b input to the rising edge of one internal pwm clock which is just after these 127 clocks. pay attention that the ic does not operate according to the configuration while the following patterns (patterns 4 and 5) are inputted. d) in case data b is inputted by the time the output of pattern 2 starts. inputting is invalid from the data a (peri od) input to the rising edge of the second internal clock. so, data b is invalid and data a is outputted. transferring data a start output 1 1 1 1 1 1 1 1 transferring data a start output transferring data a start output transferring data b start output transferring data a start output internal pwm clock pattern 1 internal pwm clock pattern 2 internal pwm clock pattern 3 internal pwm clock pattern 4 input invalid term data a output start data a period 127 127 data b output start data b period 127 127 start input invalid term data a output data a period 127 127 start data a period input invalid term data a output 127 127 start data a period input invalid term data a output start data b period
TB62D612FTG 2012-07-23 11 e) in case the period command mistakes. outputting data a does not start at the rising edge of one internal clock which is just after the data a input. outputting data b starts at the rising edge of one internal pwm clock which is just after the data b input. (7) example of data input to the different id. a) in case the data b is inputted to slave (= 02h) just after the data a is inputted to slave (= 00h). both data a and data b are outputted at the rising edge of one internal pwm clock which is just after the data a and the data b inputs. pay attention that the ic does not operate according to the configuration while following patterns (patterns 7 and 8) are input ted. b) in case period command after inputting data a to the slav e (=00h) is missed or omitted or in case period command after inputting data b to the slave (=02h) is missed or omitted. data a is outputted. da ta b is not outputted. c) in case start command is inputted after data b of pattern 7 is inputted. data a is outputted. da ta b is not outputted. 1 1 1 1 transferring data b start output transferring data a and data b. start output transferring data a start output transferring data a start output internal pwm clock pattern 8 internal pwm clock pattern 7 internal pwm clock pattern 6 internal pwm clock pattern 5 data b output start data b period start data a 127 127 input invalid term 127 slave=00h, data a slave=00h output start period start slave=002h, data b period data a output data b output slave=02h output slave=00h, data a start start slave=02h, data b 127 data a outpu t slave=00h output slave=02h output slave=00h, data a start start slave=02h, data b start 127 0 data a output slave=00h output slave=02h output
TB62D612FTG 2012-07-23 12 7. power-on reset (por) the por circuitry resets all the internal data to the def ault values upon powering up the TB62D612FTG in order to ensure proper device operation. the por circuitry is only activated when vcc rises from 0 v. to reactivate por, vcc must be powered down to 0 v. the internal data hold voltage is guaranteed after vcc has once reached or exceeded 3.0 v. 8. thermal shutdown (tsd) when the die temperature reaches 150 c , the thermal shutdown circuit is tripped, switching the constant-current outputs to off. the constant-current outpu ts are automatically turned on when the tem perature cools past the shutdown threshold. tsd trip temperature: 150 c to 180 c tsd recovery temperature: 30 c below the tsd trip temperature *please avoid positively using tsd because tsd is a detecting function of the product. vcc waveform por active por not active por active 2.0 v 1.8 v 0 v por completed reset completion voltage minimum data hold voltage initial clear
TB62D612FTG 2012-07-23 13 9. points to note when setting up the TB62D612FTG 1. external resistors for specifying the le d driving current (rext-r, rext-g, rext-b) external resistors should be separately connected to the re xt-r, rext-g and rext-b pins. three resistors must not be collectively connected to a single pin. if they are connected to a single pin, current error is generated in each rbg. 2. external resistors for id configuration the total resistance value of three external resistors used for specifying a device id (which are connected between vcc and gnd) should be about 30 k or lower. 3. id configuration sequence id configuration can be performed after por is released upon powering on. however, to avoid false operation of the id configuration, transient input signals of less than two clock cycles of the reference clock for the internal oscillator are not accepted. 4. id configuration make sure to set ids after releasing reset condition. 5 9 data configuration do not input the data which is not on the list of the data configuration table in page 6 and 7. data is written to the shift resister at the rising edge of sclk every 8 bits. and data is transferred at the falling edge of t he eighth clock. so, input data to the falling edge at the eighth clock. 6 9 special mode data which corresponds to 24 channels should be inputted. if data of more than 24 chann els are provided, the 25th and subsequent data are treated as invalid. if data of less than 24 channels are provided, those data are written to the channels in order and the remaining channels retain the previous data. 9?9 timing of data configuration in order to set data to the same slave address, next data should be inputted after 9? ms which corresponds to 127 internal pwm clocks is passed since the period command is inputted. however, in order to se t data to the different slave address, terminal of 3 ms which corresponds to 127 internal pwm clocks should not be taken. vcc 1.8v id configuration allowed id configuration not allowed id configuration not allowed 2v care should be taken during the period between the por released timing and the timing when power supply has reached the rated vcc voltage.
TB62D612FTG 2012-07-23 14 10. state transition diagram power-on vcc reaches the por release threshold voltage. id specified by the ma ster matches that of the TB62D612FTG reset=?l? reset=?h? after the TB62D612FTG is powered on, data can be programmed only after 15 ms has when the die temperature exceeds the tsd trip threshold temperature, all the outputs are disabled, while internal data is retained. /reset=?l? compares ids again exceeds the tsd trip threshold temperature cools past the tsd release threshold temperature output data is programmed for each id device using the data and clk signals for providing dimming control please refer the description from page 5 to 11 in details. reset mode internal data b id/pwm data b are reset. /reset = ?h?: data is reset forcedly. output is turned off. operation moves to low consumption mode. tsd mode (thermal shutdown) /reset=?h? :w normal mode
TB62D612FTG 2012-07-23 15 11 absolute maximum ratings (ta = 25 ) characteristics symbol rating unit supply voltage v cc 6.0 v input voltage v in -0.3 to vcc + 0.3 (note 1) v output current i out 85 ma/ch output voltage v out -0.3 to 29 v power dissipation p d 4.3 (notes 2 and 3) w thermal resistance r th (j-a) 29 (note 2) c /w operating temperature range t opr -40 to 85 c storage temperature range t stg ?55 to 150 c maximum junction temperature t j 150 c note 1: however, do not exceed 6.0 v. note 2: when mounted on a pcb (76.2 114.3 1.6 mm; cu = 30%; 35- m-thick; semi-compliant) note 3: power dissipation is reduced by 1/r th (j-a) for each c above 25 c ambient. 12 operating ranges (ta = 40 to 85 , unless otherwise specified) characteristics symbol test condition min typ. max unit supply voltage v cc ? 3 ? 5.5 v output voltage v out (on) all output 0.4 ? 4 v output current i out all output 5 ? 40 ma/ch v ih 0.7 vcc ? vcc v il sda, sclk, reset gnd ? 0.3 vcc v id0 0 ? 0.3 v id1 1/3vcc -0.3 1/3 vcc 1/3vcc +0.3 v id2 2/3vcc -0.3 2/3 vcc 2/3vcc +0.3 input voltage v id3 id0, id1, id2 vcc 0.3 ? vcc v sclk clock frequency fclk sclk (note. 4) ? ? 10 mhz data setup time tsu;dat sda-sclk (note. 4) 10 ? ? data hold time thd;dat sclk-sda (note. 4) 10 ? ? ?l? term of sclk clock tlow sclk (note. 4) 50 ? ? ?h? term of sclk clock thigh sclk (note. 4) 50 ? ? ns note. 4: please refer to below timing chart. thd;dat thigh 50% 50% 50% 50% tsu;dat sda sclk 50% tlow fclk
TB62D612FTG 2012-07-23 16 13 electrical char acteristics (ta = 25 , vcc = 4.5 to 5.5 v, unless otherwise specified) characteristics symbol test circuit test condition min typ. max unit output current i out1 4 v out = 0.4 v, r-ext = 1.2k vcc = 5 v, 12.69 13.5 14.31 ma output current accuracy between channels i out2 4 v out = 0.4 v, r-ext =1.2k all ch on vcc = 5 v, ? ? 3.0 % output leakage current i oz 4 v out = 28 v ? ? 1 a sda, sclk D D 1 i ih 1 reset(vcc=5v) 25 50 75 i il 2 sda, sclk, reset D D -1 input current i id 1,2 id0, id1, id2 D D 0.1 a changes in constant output current dependent on v cc %/vcc 4 vcc = 4.5 v to 5.5 v ? 1 2 % icc 1 3 r-ext=1.2 k ,v out =0.4 v, reset=l ? 9 14 supply current icc 2 3 r-ext = open, v out = 28.0 v ? 3 5 ma current consumption in reset mode icc (ps) 3 r-ext = 1.2 k , v out = 0.4 v, reset = h (the input current of the reset pin is excluded.) ? ? 1 a time required for a mode transition from reset mode to normal mode ton2 (*1) ` time between a high to low transition on reset and the timing when an output current is generated after input data is applied. ? ? 3 ms (*1): internal data is reset forcedly by reset command. in or der to turn on the output current, data should be inputted again. pay attention that the output current flows after pwm co unter counts its maximum (128 pwm clks) though data is inputted again. reset recovery time: 3ms (max) in case the voltage is inputted until the pwm counter counts one cycle after reset release. (after reset release, pwm counter starts from zero.)
TB62D612FTG 2012-07-23 17 14 test circuits vcc test circuit 1: high-level input current (i ih ) r ext v in = v dd a a a a vcc test circuit 2: low-level input current (i il ) a a a a vcc = 4.5~5.5 v gnd id0,1,2 sda rext-r test circuit 3: supply current f.g v ih = vcc v il = 0 v a gnd rext-r vcc = 4.5~5.5 v /outr0 /outb7 reset sclk rext-g rext-b r ext r ext r ext gnd rext-r rext-g rext-b r ext r ext id0,1,2 sda reset sclk /outr0 /outb7 /outr0 /outb7 rext-g sda reset sclk rext-b vcc vcc = 4.5~5.5 v id set id1 id0 id2 v id0 =0.3v v id1 =1/3vcc 0.3v v id0 =2/3vcc 0.3v v id0 =vcc-0.3v r ext = 1.2k r ext =1.2k r ext =1.2k
TB62D612FTG 2012-07-23 18 vcc f.g a a a v ih = vcc v il = 0 v v out = 0.4v, 28v vcc = 4.5~5.5 v sda reset sclk /outr0 /outb7 /outg1 gnd rext-r rext-g rext-b test circuit 5: switchin g characteristics c l i out vcc f.g v ih = vcc v il = 0 v v l = 5 v c l = 10.5 pf r l =300 vcc = 4.5~5.5 v sda reset sclk gnd rext-r rext-g rext-b /outr0 /outb7 id set id1 id0 id2 v id0 =0.3v v id1 =1/3vcc 0.3v v id0 =2/3vcc 0.3v v id0 =vcc-0.3v id set id1 id0 id2 v id0 =0.3v v id1 =1/3vcc 0.3v v id0 =2/3vcc 0.3v v id0 =vcc-0.3v test circuit 4: output current, output leakage current, output current accuracy, changes in constant output current dependent on v cc r ext = 1.2k r ext =1.2k r ext =1.2k r ext = 1.2k r ext =1.2k r ext =1.2k
TB62D612FTG 2012-07-23 19 15. characteristics of output current vs. external resistor (for reference) 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 [ma] ?? rext[k ] \ rext ? (vcc=5.0v, ? ta=25 ) output current ? rext external resistor output current
TB62D612FTG 2012-07-23 20 16 application circuit example c.p.u. v led sclk TB62D612FTG TB62D612FTG gnd sda sda sclk sda sclk /outr0 /outb7 00 01 10 /outr0 /outb7 id0 id1 id2 id2 11 id1id0 id=?00000000? id=?00100000? rext-r rext-g rext-b gnd rext-r rext-g rext-b vcc vcc v cc
TB62D612FTG 2012-07-23 21 package dimensions p-wqfn36-0606-0.50-001 weight: 0.083 g (typ.) (detail view of a ) a unit: mm
TB62D612FTG 2012-07-23 22 notes on contents 1. block diagrams some of the functional blocks, circu its, or constants in the block diag ram may be omitted or simplified for explanatory purposes. 2. equivalent circuits the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. timing charts timing charts may be simplified for explanatory purposes. 4. application examples the application examples provided in this data sheet are provided for reference only. thorough evaluation and testing should be implemente d when designing your applicat ion?s mass production design. in providing these application examples, toshiba does not grant the use of any in dustrial property rights. 5. test circuits components in the test circuits are used only to obtain and confirm the devi ce characteristics. these components and circuits are not guar anteed to prevent malfunction or failure from occurring in the application equipment. ic usage considerations notes on handling of ics (1) the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause br eakdown, damage or deterioratio n of the device, and may result in injury by explos ion or combustion. (2) use an appropriate power supply fuse to ensure that a large current does not continuously flow in the event of over current and/or ic fa ilure. the ic will fully break down when used under conditions that exceed its absolute maximum rating s, when the wiring is routed improperly, or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow. such a breakdown can lead to smoke or ignition. to minimize effects of a large current flow in the event of breakdown, fuse capacity, fusing time, insertion circuit location, and other such suitable settings are required. (3) if your design includes an indu ctive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current caused by inrush current at power on or the negative current caused by the back electromotive force at power off. ic breakdown may cause inju ry, smoke or ignition. for ics with built-in protection functions, use a stable power supply. an unstable power supply may cause the protection function to not operate, causing ic breakdown. ic breakdown may cause injury, smoke or ignition. (4) do not insert devices incorrect ly or in the wrong orientation. make sure that the positive and negative term inals of power supplies are connected properly. otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause breakdown, damage or deterioration of the device, which may result in injury by explosion or combustion. in addition, do not use any device that has had curr ent applied to it while inserted incorrectly or in the wrong orientation even once. (5) carefully select power amp, regulator, or other external components (such as inputs and negative feedback capacitors) and load components (such as speakers),.
TB62D612FTG 2012-07-23 23 if there is a large amount of le akage current such as input or ne gative feedback capacitors, the ic output dc voltage will increase. if this output voltage is connected to a speaker with low input withstand voltage, ov ercurrent or ic failure can cause smoke or ignition. (the over current can cause smoke or ignition from the ic itse lf.) in particular, please pay attention when using a bridge tied load (btl) connection type ic that inputs output dc voltage to a speaker directly. points to remember on handling of ics (1) heat dissipation design in using an ic with large current flow such as a power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (tj) at any time or under any condition. these ics generate heat even during normal use. an inadequate ic heat dissipation design can lead to decrease in ic life, deterioration of ic characteristics or ic breakdown. in addition, please design the device taking into consideration the effect of ic heat dissipation on peripheral components. (2) back-emf when a motor rotates in the reverse direction, stop s, or slows down abruptly, a current flows back to the motor?s power supply due to the effect of back-emf. if the current sink capability of the power supply is small, the device?s motor power supply an d output pins might be exposed to conditions beyond absolute maximum ratings. to avoid this problem, take the effect of back-emf into consideration in your system design. (3) thermal shutdown circuit thermal shutdown circuits do not necessarily pr otect ics under all circumstances. if the thermal shutdown circuits operate against the over te mperature, clear the he at generation status immediately. depending on the method of use and usage condit ions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not oper ate properly or ic brea kdown before operation.
TB62D612FTG 2012-07-23 24 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collect ively "toshiba"), reserve the right to make changes to the in formation in this document, and related hardware, software and systems (collectively "product") without notice. ? this document and any information herein may not be reproduc ed without prior written permission from toshiba. even with toshiba's written permission, reproduc tion is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for prov iding adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a ma lfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own applications, cu stomers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the precautions and condi tions set forth in the "toshiba semiconductor reliability handbook" and (b) the instructions for the application with which the product will be us ed with or for. customers are solely responsible for all aspe cts of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this product in such design or applications; (b) eval uating and determining the applicability of any info rmation contained in this document, or in c harts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operatin g parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. ? product is neither intended nor warranted fo r use in equipments or systems that require extraordinarily high levels of quality and/or reliability, and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage and/or serious public impact ( " unintended use " ). except for specific appl ications as expressly stated in this document, unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used f or automobiles, trains, ships and other transportation, traffic si gnaling equipment, equipment used to control combustions or expl osions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. if you use product for unintended use, toshiba assumes no liability for product. for details, please contact your toshiba sales representative. ? do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is pres ented only as guidance for product use. no re sponsibility is assumed by toshiba for an y infringement of patents or any other intellectual property rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provid ed in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, co nse quential, special, or incidental damages or loss, including without limitation, loss of profit s, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related so ftware or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or m anufacturing of nuclear, chemical , or biological weapons or missi le technology products (mass destruction w eapons). product and related software and technology may be controlled under the applicable export laws and regulations including, without limitat ion, the japanese foreign exchange and foreign trade law and t he u.s. export administration regulations. export and re-export of pr oduct or related software or technology are strictly prohibit ed except in compliance with all appl icable export laws and regulations. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pro duct. please use product in compliance with all applicable laws and regula tions that regulate the inclusion or use of controlled subs tances, including without limitation, the eu rohs directive. toshiba assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations.

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